About Us
The performance and reliability of power semiconductor devices are governed by a transition region only a few nanometers wide, where the semiconductor meets the gate dielectric. At the Power Device Interface Technology Laboratory, we work primarily on SiC power devices, covering the development of gate dielectric formation processes, the electrical and optical characterization of interface traps, and the analysis of the underlying physics through physical modeling and computation.
Our strength lies in completing the full research cycle — Process, Probe, Physics: creating the interface, measuring it, and explaining it — in-house, from start to finish. By moving continuously between experiment and analysis, we pursue original research that translates into better performance and reliability in power devices.
Toyama is home to a dense cluster of companies working in semiconductor devices, semiconductor production equipment, and electronic components. Through research on gate dielectric deposition, interface control, measurement, and data analysis, we aim to develop next-generation semiconductor technologies and to train researchers and engineers who will support Toyama’s semiconductor industry.

JA